1. Field of the Invention
The present invention is related to nonvolatile memories in general, and in particular, to a high-density memory element composed of trapped-charge film, being implemented with a thin body and vertical channel memory device.
2. Description of Related Art
High-density memories having two bits per cell stored in the nitride layer of ONO films or charge trap memories have been previously described in U.S. Pat. No. 6,248,633, shown in FIG. 1 and U.S. Pat. No. 6,011,725, shown in FIG. 2. In FIG. 1, the Twin MONOS device has a word gate 17 surrounded by two sidewall control gates 15 and 16. Under the control gates 15 and 16 are two memory regions 13 and 14 next to the source and drain regions 11 and 12. In FIG. 2, the memory region 23 is a single film in which charge can be stored on both edges under a control gate 24, between a source and a drain 21 and 22. Both of these patents refer to memory types that utilize a planar substrate, in that the channel region under the memory control gates is horizontal and flat.
U.S. Pat. No. 5,780,341, shown in FIG. 3, refers to a floating gate device which utilizes a non-planar substrate. The device has a word gate 34 in series with a floating gate 33, between the source and drain regions 31 and 32. Under the floating gate 33, there is a small step, or vertical element in the substrate topography. By introducing a step into the channel, CHE program efficiency is enhanced because electrons can be injected directly into the floating gate 33, in the direction of momentum, rather than by scattering.
Qimonda's IEDM 2006 structure, shown in FIG. 4 refers to a NAND trap memory in which ONO 44 is deposited over an etched thin body substrate 43. A common gate 45 wraps around the device, above the source and drain 41 and 42.
Stanford's IEDM 2007 structure, shown in FIG. 5, also refers to a FINFET device in which the substrate is etched 53 so that the memory channel is vertical. The storage element in this device is a floating gate 54 and 55.